Research Topics:

     (A) Nanoelectronics group

               Spintronics

               SL-MTJ (superlattice based MTJ) and MTJ (magnetic tunnel junctions)

               SS-MRAM (superlattice-based STT-MRAM or SL-STT-MRAM), STT- MRAM (spin-transfer torque MRAM), and MRAM (magnetoresistive random access memory) Read More

             Graphene and topological insulator, and spin-valve

          
 

     (B) Photonics group

               Photonic crystals, topological photonics, and quasicrystals

             Waveguides, integrated optics, and multilayers

             Microring resonators

             Graphene

          

SS-MRAM: A superlattice-based STT-MRAM with ultra-high performance

Our research group of the Electronics and Photonics Laboratory at National Taiwan University have developed an ultra-high performance MRAM, called SS-MARM or SL-STT-MARM. The SS-MARM can simultaneously achieve not only ultra-high MR ratio, low writing power, high-speed writing and low RA but also high endurance and simple manufacturing. Most of the shortcomings of STT-MRAM can be solved.

As we know, single crystalline (001) MgO with 0.8-3nm thickness has been used as the insulator (barrier) layer in most MRAMs, including toggle MRAM, STT-MRAM, and SOT-MRAM, since 2001. The main objective of using the MgO is to provide high magnetoresistance (MR) ratio over 200%, which is required for MRAM working. However, the crystalline MgO layer is unstable and with very large RA. The degradation of MgO caused by repeated writing will reduce the reliability and durability of STT-MRAM. Moreover, large power consumption in writing mode is required since large current passes the MgO layer. It seems impossible to find other nature insulator materials, which can provide stable structure, higher MR ratio, and lower RA for STT-MRAM.

To avoid the weakness of STT-MRAM, a superlattice (also called metamaterial or artificial material) is used to replace the MgO layer for the new type STT-MRAM, called SS-MARM or superlattice-based STT-MRAM. It is amazing that the superlattice can provide not only ultra-high MR ratio but also ultra-low RA for the SS-MARM. Research reports show that the SS-MRAM can reduce more than 90% switching power and RA value from STT-MRAM. Moreover, the MR ratio and switching speed can be increased more than 10 times when the SS-MRAM is applied. These results have been published in scientific journals, conference and reported in MRAM and IT news or website news, as shown in the following references.

It is noted that the insulator layers in the SS-MRAM are made of arbitrary amorphous material rather than single crystalline. Fabrication of the SS-MRAM becomes easier and simpler than STT-MRAM. Moreover, since stable amorphous rather than unstable crystalline is used, degradation caused by repeated writing in the SS-MRAM could be avoided. Thus, the SS-MRAM can provide greater reliability and strong endurance.

Unlike the SOT-MRAM and VC-MRAM, writing way of the SS-MRAM is not different from the STT-MRAM. Thus, no additional problems will be generated in the SS-MRAM.

MRAM has advantages when applied to the field of internet of things, artificial intelligence, machine learning and microcontrollers. Due to high performance and less weaknesses, SS-MRAM can be used to replace traditional Toggle MRAM and STT-MRAM. Moreover, SS-MRAM has the advantages of SRAM, DRAM, and Flash memory. Therefore, SS-MRAM can be applied to different fields to replace not only MRAM but also traditional memory SRAM, DRAM, and Flash. In the future, SS-MRAM will have a competitive advantage in the market for all memories of approximately $100 billion per year.

      We are now looking to collaborate with the industry to develop, test and scale-up the SS-MRAM.

 

Related publications

A.  News and Website Reports

[1] R. Mertens, 2019, “New super-lattice SL-STT-MRAM enable faster and more efficient memory architecture,” MRAM-Info, Posted: Dec 23, 2019. Read More

[2] Nanowerk News, 2020, “A superlattice based STT-MRAM with extra-high performance,” Nanowerk, Posted: Jan 17, 2020. Read More

[3] DigiTimes, 2020, “Taiwan university develops next-gen memory technology,” DigiTimes, Posted: Jun. 10, 2020. Read More

[4] 台大校訊1422:“臺大工科系薛文証教授團隊開發次世代記憶體SS-MRAMMRAM-Info以及Nanowerk News報導”(2020/2/5) 報導連結

台灣大學焦點新聞:臺大工科系薛文証教授團隊開發次世代記憶體SS-MRAM獲報導”(2020/02/10) 報導連結

臺灣大學第174期校友電子報:臺大工科系薛文証教授團隊開發次世代記憶體SS-MRAMMRAM-Info以及Nanowerk News報導”(2020/3) 報導連結

[5] 台灣大學工學院簡訊230:“【工科海洋系薛文証教授團隊】開發次世代記憶體SS-MRAMMRAM-Info專業網站撰文介紹”(2020/2/15) 報導連結

[6] DigiTimes科技網: “台大團隊突破SS-MRAM關鍵技術 搶攻次世代夢幻記憶體”(2020/6/10) 報導連結

 

B. Scientific Journals and Conferences

 

 [1] C. H. Chen and W. J. Hsueh*, 2014, “Enhancement of tunnel magnetoresistance in magnetic tunnel junction by a superlattice barrier,” Appl. Phys. Lett., Vol. 104, pp. 042405. Read More

[2] C. H. Chen, C. H. Chang, Y. H. Cheng, and W. J. Hsueh*, 2015, “Ultrahigh tunnel magnetoresistance using an artificial superlattice barrier with copper and aluminum oxide,” Europhys. Lett. Vol. 111, pp. 47005. Read More

[3] C. H. Chen, Y. H. Cheng, C. W. Ko, and W. J. Hsueh*, 2015, “Enhanced spin-torque in double-barrier magnetic tunnel junctions by a nonmagnetic-metal spacer,” Appl. Phys. Lett., Vol. 107, pp. 152401. Read More

[4] C. H. Chen, P. Tseng, C. W. Ko, and W. J. Hsueh*, 2017, “Huge spin transfer torque in a magnetic tunnel junction by a superlattice barrier,” Phys. Lett. A, Vol. 381, pp. 3124-3128. Read More

[5] A. Sharma, A. A. Tulapurkar, and B. Muralidharan, 2018, “Band-pass Fabry-Pèrot magnetic tunnel junctions,” Appl. Phys. Lett., Vol. 112, pp. 192404.  Read More

[6] P. Tseng and W. J. Hsueh*, 2018, “Enhancement of spin-transfer torque in superlattice-barrier magnetic tunnel junctions,” Global Conference on Magnetic and Magnetism Materials (GMMM 2018), July, 23-24, Osaka, Japan. Read More

[7] P. Tseng and W. J. Hsueh*, 2019, “Ultra-giant magnetoresistance in graphene-based spin valves with gate-controlled potential barriers,” New J. Phys., Vol. 21, No. 113035. Read More